VeriWell Verilog Simulator

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Last Update: 2015-08-06

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VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

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GNU General Public License version 2.0 (GPLv2)

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simulationc Edited 2014-03-01

small & quick, very well ! but it does NOT support v2001 and there are some bugs. I fixed a little and forked it to "bitbucket.org/Simuc/veriwell/".

Additional Project Details

Intended Audience

Developers

Programming Language

VHDL/Verilog

Related Categories

VHDL/Verilog Electronic Design Automation (EDA) Software

Registered

2005-09-09

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