Embodied Energy
https://chatgpt.com/share/69c07e75-5d50-8010-bba7-bba8b699f91e
| Component Group
|
Conventional Polysilicon Route
|
UMG-Si Route
|
Notes
|
|---|
| Silicon purification
|
~25–35%
|
~7–15%
|
Siemens/FBR purification is a major energy load; UMG could reduce this substantially
|
| Ingot growth, wafering, kerf loss
|
~20–30%
|
~20–30%
|
Still required even if feedstock is UMG-Si
|
| Cell processing
|
~15–25%
|
~15–25%
|
Texturing, diffusion/implant, passivation, metallization, firing
|
| Total cell-related energy
|
~65–80%
|
~45–65%
|
Includes feedstock, wafer, and finished solar cells
|
|---|
| Glass
|
~8–15%
|
~12–20%
|
Becomes more prominent when silicon purification energy falls
|
| Encapsulant, backsheet, junction box, copper, assembly
|
~8–15%
|
~12–20%
|
Mostly unchanged by UMG-Si
|
| Recycled aluminum frame
|
~2–6%
|
~3–8%
|
Much lower than primary aluminum framing
|
| Rest of finished module
|
~20–35%
|
~35–55%
|
Non-cell module materials and assembly
|
|---|
EROI
https://chatgpt.com/share/69c07e75-5d50-8010-bba7-bba8b699f91e
A mature OSE-style UMG-Si, building-integrated, inverterless DC PV system could plausibly reach system-level EROI around 100+, excluding large battery storage.
| System Boundary
|
Rough Energy Return Ratio
|
Notes
|
|---|
| Silicon purification only
|
~700
|
Based only on the 100 kW UMG-Si refining energy versus lifetime PV output
|
| Finished PV module only
|
~200–250
|
Assumes silicon purification is about one-third of total module embodied energy
|
| Building-integrated PV, no conventional racking
|
~150–220
|
Removes much of separate mounting/racking energy
|
| DC point-of-use, inverterless
|
~120–200
|
Avoids inverter embodied energy and inverter replacement losses
|
| Practical full local system, excluding batteries
|
~100–180
|
Includes module materials, junctions, wiring, controls, installation overhead
|
| Practical full local system, including batteries
|
~40–120
|
Storage dominates if batteries are large or frequently replaced
|
Physical Plant
A 10,000 ft² facility could plausibly house a 100 kW open-source UMG-Si pilot line plus low-volume wafer/cell/module prototyping, producing perhaps ~10–20 MW/year silicon-equivalent material and a smaller volume of fully finished panels unless the cell line is highly optimized - [1]. A multistory structure can achieve this on a small footprint.
| Area
|
Function
|
Rough Footprint
|
|---|
| Silicon refining bay
|
Remelt, slag refining, vacuum refining, directional solidification
|
1,500–3,000 ft²
|
| Crushing / sizing / feed prep
|
MG-Si or UMG-Si prep, classification, storage
|
500–1,000 ft²
|
| Wafer handling / crystal prep
|
Cutting, cropping, cleaning, inspection
|
1,000–2,000 ft²
|
| Small cell process area
|
Texturing, diffusion/passivation, metallization, firing
|
2,000–4,000 ft²
|
| Module assembly
|
Stringing, layup, lamination, framing or frameless assembly, testing
|
1,500–3,000 ft²
|
| QC / assay / metrology
|
Electrical testing, microscopy, sample prep, outsourced assay staging
|
500–1,000 ft²
|
| Utilities / storage / safety
|
Cooling, gases, electrical, PPE, consumables, maintenance
|
1,000–2,000 ft²
|
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