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A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
Features
- Drawing, editing and printing of diagrams
- Binary, ASCII and "free text" condition codes
- Integrity check
- Interactive simulation
- HDL export in the file formats: AHDL, VHDL, Verilog HDL, KISS
- Creation of VHDL test code
- EPS, SVG, PNG diagram export
- State table export in Latex, HTML and plain text format
- State Machine Compiler (SMC) export
- Ragel file export
- Other export formats: SCXML, vvvv Automata code
Project Samples
