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compliance-testing

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Synthesizable 3-stage pipelined RV32E RISC-V processor core in SystemVerilog-2012 for Artix-7 FPGA (Nexys 4) and ASIC. Features hazard forwarding, 32KB BRAM, MMIO LED peripherals, 100% RISC-V ACT 4.0 compliance (195/195 tests passed), live silicon validation, and ongoing ECC SEC-DED fault-tolerance & Cadence Genus ASIC synthesis extensions.

  • Updated Aug 1, 2026
  • Assembly

Fictional digital-asset custody mock built to be tested: a four-layer Playwright + TypeScript architecture (Zod contract oracle, deterministic workflows, thin UI, required compliance gate), a planted-defects demo branch the suite catches red-handed, a self-auditing agent panel, and a perf layer proving contention correctness on SQLite.

  • Updated Jul 20, 2026
  • TypeScript

When Aristotle gets a LinkedIn account and starts red-teaming LLMs. System-prompt attack surface testing using first-principles axiom framework. Load it. Ask something terrible. Watch what happens.

  • Updated Mar 16, 2026

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