VREDUCESD — Perform a Reduction Transformation on a Scalar Float64 Value

Perform a reduction transformation of the binary encoded double precision floating-point value in the low qword element of the second source operand (the third operand) and store the reduced result in binary floating-point format to the low qword element of the destination operand (the first operand) under the writemask k1. Bits 127:64 of the destination operand are copied from respective qword elements of the first source operand (the second operand).

The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-point source value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduc-tion transformation can be expressed as: M -M dest = src – (ROUND(2 *src))*2 ; M where “Round()” treats “src”, “2 ”, and their product as binary floating-point numbers with normalized significand and biased exponents. p The magnitude of the reduced result can be expressed by considering src= 2 *man2, where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent p-M-1 Then if RC = RNE: 0<=|Reduced Result|<=2 p-M Then if RC ≠ RNE: 0<=|Reduced Result|<2 This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision Exception, which is imm8[3]=1), no precision exception is reported.

The operation is write masked.

Handling of special case of input values are listed in Table 5-27.

ReduceArgumentDP(SRC[63:0], imm8[7:0])
{
    // Check for NaN
    IF (SRC [63:0] = NAN) THEN
        RETURN (Convert SRC[63:0] to QNaN); FI;
    M ← imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
    RC ← imm8[1:0];// Round Control for ROUND() operation
    RC source ← imm[2];
    SPE ← imm[3];// Suppress Precision Exception
                -M
                            M
                            M
    TMP[63:0] ← 2 *{ROUND(2 *SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2 as standard binary FP values
    TMP[63:0] ← SRC[63:0] – TMP[63:0]; // subtraction under the same RC,SPE controls
    RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
}

IF k1[0] or *no writemask*
    THEN
            DEST[63:0] ← ReduceArgumentDP(SRC2[63:0], imm8[7:0])
    ELSE
        IF *merging-masking*
                            ; merging-masking
            THEN *DEST[63:0] remains unchanged*
            ELSE ; zeroing-masking
                THEN DEST[63:0] = 0
        FI;
FI;
DEST[127:64] ← SRC1[127:64]

VREDUCESD __m128d _mm_mask_reduce_sd( __m128d a, __m128d b, int imm, int sae)
VREDUCESD __m128d _mm_mask_reduce_sd(__m128d s, __mmask16 k, __m128d a, __m128d b, int imm, int sae)
VREDUCESD __m128d _mm_maskz_reduce_sd(__mmask16 k, __m128d a, __m128d b, int imm, int sae)

Invalid, Precision.

If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

See Table 2-49, “Type E3 Class Exception Conditions.”

Source: Intel® 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes (Order Number 325462-091US, March 2026)
Generated: 7-6-2026