GATE | CS | 2012 | COA | Cache Memory | Question 54

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A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is

11

14

16

27

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GATE CS 2012,Computer Organization and Architecture,Cache and main memory,Computer Organization and Architecture GATE CS PYQs
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