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Commits on Dec 28, 2015

• Import the simplified MemStore from Project Sexain-MemController

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Commits on Dec 22, 2015

• Add documents and cite Project Sexain-MemController in README

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Commits on Dec 12, 2015

• Import AddrTransTable from Project Sexain-MemController

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Commits on Dec 11, 2015

• Import VersionBuffer from Project Sexain-MemController

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Commits on Dec 8, 2015

• Import Profiler from Project Sexain-MemController

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Commits on Dec 7, 2015

• Import IndexQueue from Project Sexain-MemController

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Commits on Nov 12, 2015

• Modify README and state the current status of this repo

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Commits on Oct 10, 2015

• Tweak the THNVM config script to have hybrid memory

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• Add new options and a function to config DRAM+PCM hybrid memory

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• Add the class of virtual crossbar for logic connection purpose

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• Duplicate configs/example/se.py as a base for THNVM's config script

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• New class for DDR3-based PCM

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Commits on Oct 6, 2015

• Modify .gitignore to ignore trivial files

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Commits on Oct 5, 2015

• Set up private L2 caches and a L3 shared cache

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• Add the L3 cache option and change default cache sizes

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• Set cache properties

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Commits on Oct 4, 2015

• Add the hash table benchmark

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• Import latest gem5-stable (snapshot@10874)

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• Initial commit

  

  Jinglei Ren

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