Abstract
Quantum random access memory (QRAM) enables efficient access to classical data for quantum computers and is a prerequisite for many quantum algorithms in achieving quantum speed-up. Despite various proposals, there have not been many experimental realizations of QRAM. Here we use a superconducting quantum processor to implement a circuit-based bucket-brigade QRAM, which uses a binary tree of quantum routers to enable efficient addressing of the stored information. To facilitate the experimental implementation, we introduce an efficient gate decomposition scheme for quantum routers, which effectively reduces the depth of the QRAM circuit compared with the conventional controlled-SWAP implementation. We further propose an error mitigation method to improve the query fidelity of the QRAM. With these techniques, we are able to experimentally implement the QRAM architectures for addressing four and eight classical bits, achieving query fidelities up to 0.809 ± 0.025 and 0.604 ± 0.005, respectively. Additionally, we study the error propagation mechanism and the scalability of our QRAM implementation, which provides experimental evidence for the noise resilience of the bucket-brigade architecture. Our results highlight the potential of superconducting quantum processors for realizing a scalable QRAM architecture.
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Data availability
The data presented in the figures and that support the other findings of this study are publicly available via Zenodo at https://doi.org/10.5281/zenodo.18408759 (ref. 45.) Source data are provided with this paper.
Code availability
The data analysis and numerical simulation codes for this study are publicly available via Zenodo at https://doi.org/10.5281/zenodo.18408759 (ref. 45).
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Acknowledgements
We thank H. Wang for supporting the device and the experimental platform on which the experiment was carried out. The device was fabricated at the Micro-Nano Fabrication Center of Zhejiang University. We acknowledge support from the National Key Research and Development Program of China (Grant No. 2023YFB4502600), the Zhejiang Provincial Natural Science Foundation of China (Grant Nos. LR25F020002, LR24A040002 and LDQ23A040001), the National Natural Science Foundation of China (Grant Nos. 12174342, 12274368, 12274367, 12322414, 12404570, 12404574 and 92365301).
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C.S., L.L., Z.W. and J. Yin conceived the project. F.S. conducted the experiments under the supervision of C.S. Y.J. designed the experimental circuits and performed the theoretical analyses under the supervision of C.S. Y.J., F.S. and D.X. performed the simulations and analysed the experimental data under the supervision of C.S. and L.L. H.L. fabricated the device. C.S., Z.W., Q.G., H.L., P.Z., Y.W., K.W., C.Z., A.Z., Y.Z., Y.G., Z.C., G.L., J. Yang and Y.H. contributed to the experimental set-up. Y.J., F.S., D.X., L.L. and C.S. wrote the paper with input from all authors. All authors discussed the results and contributed to the final version of the paper.
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Nature Physics thanks Connor Hann, Sébastien Léger and Hong Qiao for their contribution to the peer review of this work.
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Extended data
Extended Data Fig. 1 Illustration of the query process of two-layer QRAM.
which provides a detailed explanation of Fig. 1d, elucidating the role of each physical qubit in every phase and the operations performed. Address preparation:The initial address state is prepared on the two address register qubits, a0 and a1. Address loading:The qubit originally holding a0 is reassigned as the router address qubit A. A quantum routing operation is then applied to load the information from a1 into the second-layer router address qubits A0 and A1. Finally, a SWAP gate moves A to the qubit originally occupied by a1. Data loading:The router data qubit D is initialized to \(|+\rangle\) to enable phase encoding during data writing. Its state is then loaded into the second-layer router data qubits D0 and D1 via a quantum routing operation. Data writing:Classical bits are encoded by selectively applying or omitting the quantum gates inside the dashed squares, depending on the bit value (1 or 0). Data retrieval:The quantum state is retrieved from D0 and D1 back to D via quantum routing. A Hadamard gate is applied to D to return the state to the computational basis. Quantum teleportation is then used to transfer the state from D to the data register qubit d. Address retrieval: A is swapped back to the qubit originally holding a0. The address information in A0 and A1 is then retrieved back to the qubit initially holding a1 via a quantum routing operation. Error mitigation and quantum state tomography (QST): QST is applied to a0, a1, and d, with the tomography operation on d reinterpreted via Pauli tracking (see Methods). Router qubits are also measured for post-selection error mitigation.
Extended Data Fig. 2 The proportion of valid results after error mitigation in the two-layer bucket-brigade QRAM.
In all figures, the proportion values represent the average value of the proportion of valid results across the 16 classical data configurations, with the error bar representing their standard deviation. a, The proportion of valid results after error mitigation for a two-layer bucket brigade QRAM under varying query addresses. b, The proportion of valid results for different error mitigation strategies under query addresses \(|0+\rangle\) and \(|1+\rangle\).
Extended Data Fig. 3 Experimental construction of the three-layer bucket-brigade QRAM.
a, Schematic of the three-layer bucket-brigade QRAM, which can query eight classical data bits, labeled from x000 to x111, according to the query address. b, Device layout for implementing the three-layer bucket-brigade QRAM. Physical qubits are labeled according to their assigned roles during operational phases from address loading to address retrieval. c, Quantum circuit for the error scaling experiment of the three-layer QRAM. As in the two-layer QRAM case, the router address qubit (A), router data qubit (D), and one ancilla qubit are reused as the address register a0, a1, and a2 at the beginning and end of the experiment. Instead of using quantum teleportation, here the data bus is directly transferred from the router data qubit D to the data register qubit d via two SWAP gates at the end of the data retrieval phase. a, Schematic of the three-layer bucket-brigade QRAM, which can query eight classical data bits, labeled from x000 to x111, according to the query address. b, Device layout for implementing the three-layer bucket-brigade QRAM. Physical qubits are labeled according to their assigned roles during operational phases from address loading to address retrieval. c, Quantum circuit for the error scaling experiment of the three-layer QRAM. As in the two-layer QRAM case, the router address qubit (A), router data qubit (D), and one ancilla qubit are reused as the address register a0, a1, and a2 at the beginning and end of the experiment. Instead of using quantum teleportation, here the data bus is directly transferred from the router data qubit D to the data register qubit d via two SWAP gates at the end of the data retrieval phase.
Extended Data Fig. 4 Error budget for the three-layer QRAM query infidelity.
The results are obtained via numerical simulations with address state \(|00+\rangle\) and the classic configuration 01010101. The percentage in parentheses represents the proportion of this error component in the total error. CZ: CZ gate depolarizing error, excluding the decoherence error during CZ gates; 1Q: Single-qubit gate depolarizing error, excluding the decoherence error during single-qubit gates; T1: Qubit energy relaxation error; Tφ: Qubit dephasing error. See Supplementary Information for details on the error budget analysis.
Extended Data Fig. 5 Simulated query infidelity versus two-qubit gate error rate.
The simulation data are fitted to 1 − F = A × pα, where F is the query fidelity and p is the two-qubit gate error rate. Only data points with infidelity below 0.1 are included in the fit. Experimental results for both two- and three-layer QRAM at p = 3.8 × 10−3 are marked by pentagrams. The discrepancy between the experimental and numerical results is mainly due to the over-simplification of the error models employed in the numerical simulation (see Method).
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Shen, F., Ji, Y., Xiang, D. et al. A bucket-brigade quantum random access memory. Nat. Phys. 22, 745–750 (2026). https://doi.org/10.1038/s41567-026-03218-2
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DOI: https://doi.org/10.1038/s41567-026-03218-2
